Step by Step Guide from Scratch

What you'll learn

Essential principles of AXI Stream, AXI Lite and AXI Full.
Implementation of AXI Stream, AXI Lite and AXI Full master and slave from scracth.
Implementation of AXI Burst modes in Verilog.
Implementation of AXIS Arbiter, AXIS FIFO and AXI Lite GPIO from scratch.

Requirements

Basics understanding of Verilog and Digital Electronics

Description

AXI (Advanced eXtensible Interface) is widely used in System-on-Chip (SoC) designs because it provides a highly efficient and flexible interconnect solution for complex systems.Master the essentials of the AXI protocol with our hands-on course, designed to provide in-depth knowledge of AXI fundamentals in Verilog. With 95% coding and only 5% theory, the focus is on practical, real-world skills. You will explore the signals of AXI Stream, AXI Lite, and AXI Full interfaces and build AXI Master and Slave components from scratch. Learn to implement various burst modes, verify AXI transactions using the AXI protocol checker, and design advanced components like AXI Stream FIFOs, arbiters, and AXI Lite GPIO modules. The course emphasizes coding practice while offering essential theoretical insights to strengthen your understanding of AXI's intricacies. Ideal for design and verification roles, this training equips you with the skills to excel in your career and confidently tackle challenging interviews. Whether you're a beginner or an experienced professional looking to sharpen your expertise, this course provides a comprehensive learning experience. In addition, you'll gain exposure to real-world applications of AXI in complex systems, enhancing your ability to design, debug, and verify AXI-based solutions. Enroll now to gain the knowledge and hands-on experience needed to master AXI in Verilog and take a significant step forward in your VLSI journey.

Who this course is for

A VLSI engineer is interested in constructing Custom AXI peripheral in Verilog for SoC.
Homepage:

https://www.udemy.com/course/communication-series-p3-amba-axi-in-verilog/