Video Training →VSD - Functional Verification Using Embedded-Uvm - Part 1

What you'll learn
SoC design flow, role of Functional Verification
Logic Modeling, Introduction to Verilog
Concept of Hierarchy, Simulation-Time, and Concurrency in Hardware Modeling
Simulation Technology, Discrete Event Simulation
Verification Trends and Challenges
Concepts and Principles of Functional Verification
Testbench Architecture and Components
Lab – Tool Setup and Usage -- a simple DUT with traditional Verilog testbench will be provided with a Makefile to compile and simulate – Debug using waveforms
Requirements
Should be good with digital electronics
Should be good with Linux/UNIX basic commands
Description
Now here's a course, "hand-crafted" for anyone and everyone, who want to move from back-end to front-end OR for people just curious to know and learn, what exactly happens in field of VLSI verification. The reason its "hand-crafted" is because it starts from very basics and in coming parts of this course, things will slowly move towards advanced level UVM.Another reason for this course to be "hand-crafted" is due to the open-source tool used to cover labs introduced in this course. This is Part - 1 in the "Verification Series". This part will cover SoC design flow, basics of functional verification, trends and challenges, introduction to open-source Embedded-UVM, emulation, and the DUTAbout Embedded-UVM:Embedded UVM is an opensource implementation of IEEE 1800.2 standard of Universal Verification Methodology. In this webinar, we take a dive into Embedded UVM and its use cases as a platform for Functional Verification and SoC-FPGA based Emulation.About Speaker:Puneet Goel is a 1994 graduate in Electronics from Punjab Engineering College. He has 24 years of experience in the VLSI industry where he worked for STMicro, Motorola, Texas Instruments and TranSwitch. For the past 8 years, he has been working for Coverify Systems Technology, where he provides verification services and works on creating viable opensource solutions for chip verification. Puneet is the main developer of Embedded UVM.
Overview
Section 1: E-UVM Installation procedures
Lecture 1 E-UVM Installation Procedure - Part 1
Lecture 2 E-UVM Installation Procedure - Part 2
Section 2: Introduction to verification frame-work
Lecture 3 Introduction to Makefile concept and labs
Lecture 4 Introduction to functional spec and behavioral description
Lecture 5 Introduction to typical System-On-Chip
Lecture 6 Introduction to functional simulation and TLM simulation
Lecture 7 Basics of hardware, software, virtual platform and algorithms
Lecture 8 More information about virtual platforms
Lecture 9 Classification and conclusion of tasks involved in frontend and backend
Section 3: Verification Trends And Challenges
Lecture 10 Introduction to SoC FPGA
Lecture 11 Why the world needs more verification?
Lecture 12 Corollary of Moore's Law and its significance
Lecture 13 Repercussions of Moore's Law on verification
Lecture 14 Why the need of System Verilog and not Verilog ?
Lecture 15 Verification tool performance and take-aways
Lecture 16 Simulation vs Emulation and concept of multi-threading
Section 4: The need of the hour : Embedded-UVM
Lecture 17 Multi-core processor throughput vs latency and why E-UVM?
Lecture 18 More on multi-threading and world-wide initiatives on open-source verification
Lecture 19 More details and opportunities on open-source verification
Lecture 20 Present and future of programmable hardware
Lecture 21 How programmable hardware will be verified in future?
Section 5: Conclusion
Lecture 22 Open-source hardware is not free
Lecture 23 Implications of FPGA in future
Beginner electronics student, curious to know about verification,Professional from a different back-ground of VLSI, but wants to learn VLSI verification methodologies,Anybody looking to change domain to Verification from other VLSI domains


Homepage

https://www.udemy.com/course/functional-verification-using-embedded-uvm-part-1/