Video Training →Udemy - State Machine Design Basics in VHDL for Absolute Beginners

What you'll learn
Moore State Machine & Mealy State Machine Design using VHDL
Requirements
Basic Knowledge of Digital Logic Design & Basic knowledge of VHDL Programming
Description
Hello Dear Student ,
This Course - State Machine Design is using Design Implementation using VHDL Programming .
This Course is targeted for Absolute Beginners in the Domain of State Machine Design & it covers the Basic Level Contents of Moore State Machine , Mealy State Machine / FSMs using VHDL Programming .
Although this Course is for Absolute Beginners in the Domain of State Machine Design , It is expected that you should have little understanding of , Digital - Combinational & Sequential Logics and some basic knowledge of VHDL Programming .
After completion of this Course & after referring some Books on State Machine Design , you may further study and plan even to construct the Complex State Machine Designs like small RISC Processor Design / Micro-controller Logic or any sequential processing Logic Block / Module / Digital System .
This Course is focused on Basic Logical Concepts of Constructing State Machine Design using VHDL , but is not much focused on the Physical Timing Optimization issues of the Design.
I hope you will enjoy , learning this Course .
Pravinkumar P. Ambekar
Who this course is for:
Students of Engineering , Polytechnic , Hobbyists who wish to develop Programmable & Sequential Logic of his/her own

Homepage

https://www.udemy.com/course/state-machine-design-basics-in-vhdl-for-absolute-beginners/