E-Books →Digital System Design With SystemVerilog

To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)-and today's most powerful, useful HDL is SystemVerilog, now an IEEE standard.Digital System Design with SystemVerilogis the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it.
Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog-from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org.
Coverage includes
- Using electronic design automation tools with programmable logic and ASIC technologies
- Essential principles of Boolean algebra and combinational logic design, with discussions of timing and hazards
- Core modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkers
- Sequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliers
- Designing finite state machines: from ASM chart to D flip-flops, next state, and output logic
- Modeling interfaces and packages with SystemVerilog
- Designing testbenches: architecture, constrained random test generation, and assertion-based verification
- Describing RTL and FPGA synthesis models
- Understanding and implementing Design-for-Test
- Exploring anomalous behavior in asynchronous sequential circuits
- Performing Verilog-AMS and mixed-signal modeling
Whatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilog's full power and use it to the fullest.