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E-BooksAnalog Circuit Design for Process Variation-Resilient Systems-on-a-Chip



Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip
Analog Circuit Design for Process Variation-Resilient Systems-on-a-Chip by Marvin Onabajo
English | PDF | 2012 | 182 Pages | ISBN : 1461422957 | 7.1 MB
This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements.


This book describes several techniques to address variation-related design challenges for analog blocks in mixed-signal systems-on-chip. The methods presented are results from recent research works involving receiver front-end circuits, baseband filter linearization, and data conversion. These circuit-level techniques are described, with their relationships to emerging system-level calibration approaches, to tune the performances of analog circuits with digital assistance or control. Coverage also includes a strategy to utilize on-chip temperature sensors to measure the signal power and linearity characteristics of analog/RF circuits, as demonstrated by test chip measurements.
Describes a variety of variation-tolerant analog circuit design examples, including from RF front-ends, high-performance ADCs and baseband filters;
Includes built-in testing techniques, linked to current industrial trends;
Balances digitally-assisted performance tuning with analog performance tuning and mismatch reduction approaches;
Describes theoretical concepts as well as experimental results for test chips designed with variation-aware techniques.



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